The present invention relates generally to interconnect devices such as a cross bar switches that connect processors to memory in multiprocessor computer systems, and particularly, to an arbitrating system and methodology for improving low latency through the crossbar switch for increasing performance of parallel computers.
To achieve high performance computing, multiple individual processors have been interconnected to form a multiprocessor computer system capable of parallel processing. Multiple processors can be placed on a single chip, or several chips—each containing one or more processors—become interconnected to form single- or multi-dimensional computing networks into a multiprocessor computer system, such as described in co-pending U.S. Patent Publication No. 2009/0006808 A1 corresponding to U.S. patent application Ser. No. 11/768,905, the whole contents and disclosure of which is incorporated by reference as if fully set forth herein, describing a massively parallel supercomputing system.
Processors in a multiprocessor computer system, such as a massively parallel supercomputing system, typically implement some form of arbitration when communicating signals for storage in a memory through a cross bar interconnect.